Effect of annealing on the electrophysical properties of CdTe/HgCdTe passivation interface by the capacitance–voltage characteristics of the metal–insulator–semiconductor structures

The capacitance–voltage characteristics of metal–insulator–semiconductor structures based on Hg_1xCd_xTe (x = 0.218) with CdTe passivation are studied before and after the passivation annealing process. We found that after vacuum annealing at 300 °C for 24 h, the micromorphology of the passivation layer was significantly improved, and as the fixed charge density decreased from 1.3 × 10¹² cm² to 1.0 × 10¹⁰ cm², the fast surface state density decreased from 2 × 10¹³ cm² eV¹ to 3 × 10¹² cm² eV¹, with a minimum value of 1.2 × 10¹¹ cm² eV¹. From these findings, combined with the secondary ion mass spectroscopy analysis, we conclude that the annealing process propagates an equivalent electrical surface for CdTe/HgCdTe uniformly from the principal physical interface to the inside of the bulk material, effectively improving the characteristics of the CdTe passivation layer. 

SEM image of the CdTe/HgCdTe interface 

https://aip.scitation.org/doi/10.1063/5.0021073